Professor Hiromi Hiraishi

Area and Subject Taught Logic Design
Research Theme(s) Formal Design Verification of Logic Systems
Academic Degrees Doctor of Engineering, Kyoto University
Keywords for Research Field Logic Design, Design Verification, Parallel Computation
Office Phone Number 81-75-705-1901

Research Overview

There is a significant danger of design errors when developing large-scale or complex systems. If the design errors are overlooked and the system is put into service, it can result in situation that is extremely detrimental to society: well-known examples include the power outages that occurred in the American Northeast, failures in the online systems used by banks, and interruptions in mobile phone service. With the extraordinary advances being made in computer technology, it has become commonplace for computers to be embedded in everyday products such as electrical household appliances. It is becoming increasingly important to verify the correctness of the design when developing such logic systems. Conventional design verification methods center on computer simulations of the operation of the system being designed; however, such methods cannot simulate all operation patterns, and there is a high possibility that design errors may be overlooked. I am researching ways to avoid this sort of situation by using mathematical techniques to verify design correctness automatically. Thus far I have succeeded in verifying the designs of parallel computer connection configurations and programs for controlling robots.

Notable Publications and Works in the Last Three Years

  1. Mori and Hiraishi: “Input Pattern Parallel Logic Simulation of Combinatorial Circuits Using GP-GPU (in Japanese)”, Acta Humanistica et Scientifica Universitatis Sangio Kyotiensis, Natural Science Series, No. 42, pp.63-70, March 2013.
  2. Hiraishi: "Optimum Ordering Algorithm Suitable for Cluster System Based on Parallel Branch and Bound Method and Dynamic Division of Search Tree (in Japanese)", IPSJ Trans. Advanced Computing Systems, Vol.46, No.SIG12 (ACS11), pp.330-337, Aug. 2005.
  3. Watanabe and Hiraishi: "Debugging Support Tool for Message Passing Parallel Programs Based on Visualization of Communication History (in Japanese)", Bulletin of the Institute of Advanced Science and Technology of Kyoto Sangyo Univ., No.3, pp.21-40, July 2004.